HP ProLiant Servers AIS : Server Chipsets (part 1) - Original Server Architecture, Dual Independent Buses, Bus Mastering, MIOC Architecture

10/11/2012 3:21:12 AM

1. Original Server Architecture

The original PC system architecture started out with one bus with a single speed and the same bus width to all peripherals, as illustrated in Figure 1.

Figure 1. Original PC system architecture.

Two main performance bottlenecks resulted from this architecture. First, because only one system bus was available for all devices, only one device could use the system bus at a time. When one device was using the bus, all other devices had to wait their turn for attention. Second, all bus transfers, both system and I/O, were restricted to the same bus speed.

In this architecture, approximately 96% of all data transfers were between the processor and memory.

2. Dual Independent Buses

To alleviate the problems caused by a single system bus, the next step was to split the bus into two independent buses. This was known as dual independent bus architecture. This architecture is shown in Figure 2.

Figure 2. Dual independent bus architecture.

HP introduced the first dual independent bus design. This design allowed the memory bus between the processor and memory to operate at a higher speed than that of the I/O expansion bus. An I/O bridge was used to synchronize data transfers between the two buses.

In this architecture, the bottleneck now shifted to the I/O bridge. All I/O devices were contending with the I/O bridge to communicate with the host bus. To solve this problem, buffers were added to the bridge. If the bridge was busy transferring data from one I/O device, it would buffer the data from other I/O devices. When the bus was free, the bridge sent the buffered data. This enabled the I/O devices to continue working and not wait for a response from the bridge.

3. Bus Mastering

The next step in server evolution was bus mastering technology, as illustrated in Figure 3.

Figure 3. Bus mastering.

With bus mastering, multiple bus master devices contended for access to system memory. Multiple processors could transfer data directly to main memory. I/O adapters could also transfer data directly to main memory.

Although enabling I/O devices to be bus masters freed up processor resources, it caused contention for memory.

4. MIOC Architecture

The problem of memory contention was solved when HP introduced the first data-flow manager, a tri-bus arbitrator that acted as a memory and I/O controller (MIOC). This architecture is illustrated in Figure 4.

Figure 4. MIOC architecture.

The data-flow manager provided three main functions: (1) bus arbitration; (2) timing; and (3) buffering between the processor, memory, and I/O.

In this architecture, the width of the memory bus was increased to 128 bits to allow multiple concurrent I/O transactions.
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