At the most basic level, a
processor is a group of components that execute instructions. An
instruction is an order (such as add, subtract, or compare) that a
computer program gives to a processor. Instructions are written in
binary code, which means they are represented by 1s and 0s. The binary
code opens and closes gates between two devices in the processor that
need to communicate with each other. This process moves information from
one device to the other.
Typically, a programmer
creates a new application with a high-level programming language.
Commands in the high-level programming language correspond to several
instructions. When the programming is complete, a compiler converts the
high-level program into instructions. This process is illustrated in Figure 1.
1. Processor Components
The key components in a processor are illustrated in Figure 2, and are described as follows:
Prefetch unit—
A holding place for instructions and operands that a processor will need.
Decode unit—
A component that breaks an instruction into its constituent parts.
Execution unit—
A component that performs the actual data processing, such as
adding and subtracting. The execution unit can be further divided into
two other components: (1) the arithmetic logic unit (ALU), and (2) the floating-point unit (FPU).
Control unit—
A component that acts as a scheduler for the execution units.
Registers—
A small number of memory locations used by the control and execution units to store data temporarily.
Level 1 (L1) cache—
A small, fast memory area that holds recently used instructions and data.
Note
Some processors are designed around the Harvard architecture. In this architecture, the L1 cache is divided into an
instruction cache
(Icache) and a separate
data cache
(Dcache), as shown in the graphic.
Branch target buffer—
A register that stores recently taken branches to aid in branch prediction.
Bus interface unit—
A component that controls access to the address and data buses.
2. How Processors Handle Instructions
In general, a processor goes through five stages when it receives input.
2.1. STAGE 1: FETCHING INSTRUCTION
The prefetch unit
searches for an instruction to handle the input. First it looks for an
instruction in the L1 cache (or the Icache portion of L1). If it does
not find the instruction there, the prefetch unit looks for it in
successive layers of the memory hierarchy.
After the correct
instruction is found, it is stored in the L1 cache. The prefetch unit
fetches the instruction from the cache and sends it to the decode unit.
2.2. STAGE 2: DECODING INSTRUCTION
The decode unit
breaks the instruction into its basic elements, such as an index, data,
and the operation code. The decode unit sends the decoded result to the
control unit.
2.3. STAGE 3: EXECUTING INSTRUCTION
The control unit sends the
decoded instruction to an execution unit, such as the ALU. The execution
unit completes the command, such as adding, subtracting, multiplying,
and dividing.
2.4. STAGE 4: TRANSFERRING DATA
If the instruction is a
command, the data it needs to complete the command is transferred to the
execution unit from the registers.
2.5. STAGE 5: WRITING DATA
If required, the execution unit writes the result to a register and data cache.
3. Clock Synchronization
| | Clock Cycle 1 | Clock Cycle 2 | Clock Cycle 3 | Clock Cycle 4 | Clock Cycle 5 | Clock Cycle 6 | Clock Cycle 7 | Clock Cycle 8 | Clock Cycle 9 | Clock Cycle 10 |
|---|
| Instruction 1 | Fetch instruction | Decode instruction | Execute instruction | Fetch data | Write data | | | | | |
| Instruction 2 | | | | | | Fetch instruction | Decode instruction | Execute instruction | Fetch data | Write data |
Each
stage that the processor goes through is synchronized with the system
clock. If each stage takes one clock cycle to complete, one instruction
will be processed in five clock cycles. After five cycles, the next
instruction can be processed
